The present invention relates, in general, to the field of integrated circuit dynamic random access memories (“DRAMs”). More particularly, the present invention relates to a DRAM memory architecture that allows reading or writing from outside the integrated circuit while transferring or reading data from the same addressed memory cell to a second DRAM subarray.
Conventional single port (“1T/1C”) DRAM cells and associated memory architectures are known in the art. Dual port (“2T/1C”) DRAM cells or dual port video RAMs are also known in the art. These dual port video RAMs contain a high speed serial port and a conventional multibit parallel port. One problem with prior art memory cells and architectures is that they only allow one operation such as reading or writing to occur at a time.
Referring now to FIG. 1, a prior art memory architecture 10 is shown including a first set 22 of data lines (INT I/O and complementary INT I/O), DRAM subarrays 12A and 12B, sense amplifier blocks 14A and 14B, as well as row decoding circuits 16A and 16B, and column decoding circuits 18A and 18B. Selection transistors M0 and M1 are used to transfer the sensed data from DRAM subarrays 12A and 12B to data lines 22 upon operation of the “SEL 0” control signal. Similarly, selection transistors M2 and M3 are used to transfer the sensed data from DRAM subarray 12B to data lines 22 upon operation of the “SEL 1” control signal. For the sake of clarity in FIG. 1, the interconnecting bit and word lines are not shown.
Turning now to FIG. 2, a prior art block diagram shows further details of a sense amplifier block 14. As is known in the art, sense amplifier block 14 includes a plurality of sense amplifiers 20A through 20N. Each sense amplifier is coupled to two coupling transistors for transferring the sensed data from the DRAM subarrays to lines 15 and 17, which are coupled to the selection transistors as previously described.
Referring back to FIG. 1, in the prior art memory architecture 10, either the SEL 0 or SEL 1 signals go high to put data from one sense amplifier band 14A or 14B onto the data lines 22. What is not possible is to internally read or transfer that same data, or other data, to any other DRAM subarray.
What is desired, therefore, is a memory architecture that allows reading or writing from outside the integrated circuit while transferring or reading data from the same addressed memory cell to a second DRAM subarray or to transfer data between unrelated DRAM subarrays.